1. Field of the Invention
The present invention relates to a method for generating test patterns utilized in manufacturing a semiconductor device. The present invention also relates to a computer readable medium, a method for making a photo mask, and a method for manufacturing a semiconductor device, which are associated with a method for generating test patterns.
2. Description of the Related Art
In manufacturing semiconductor integrated circuits, the integration degree of devices formed in wafers is increased, and the design rule thereof is miniaturized. Consequently, influences of an optical proximity effect (OPE) have become prominent such that patterns are not transferred onto wafers in predetermined shapes or sizes. This problem requires a certain technique, such as optical proximity effect correction (OPC) or process proximity effect correction (PPC), which is performed on a mask to compensate for a process conversion difference due to the OPE, thereby ensuring that transferred shapes agree with predetermined design patterns. Use of the OPC or PPC makes it possible to suppress fluctuations in the critical dimension (CD) on a wafer, so that miniaturized patterns on the wafer are faithful to the design (for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-294551). Further, there are proposed or performed resolution enhancement techniques (RET) for improving resolution by adjusting the illumination and/or mask, such as insertion of auxiliary patterns smaller than the resolution limit (sub resolution assist feature: SRAF), a phase shift mask of the Levenson type, polarized illumination, and multi-phase light exposure.
Where mask data is created, at first, all the necessary verifications and/or corrections are applied to design data, and the data thus prepared is once fixed and taped out. Then, the data is subjected to various types of processes, such as OPC, to create mask data, in a mask data process. Then, the data is verified by a simulation of lithography and/or transfer onto wafers. As a result, pattern configurations (marginless points) may be found to bring about problems such that the process yield will be low due to open/short defects and process margins will come short. If a pattern configuration including a marginless point is present, and its criticality is high enough to require correction, the correction has to be made back to a design data level. In this case, it is necessary to re-perform various types of verification and process, such as design rule checking before tape-out, data transmission, data reception examination, mask data process, OPC, and mask data verification. This deteriorates the turnaround time (TAT) and cost of data preparation.
Accordingly, uncorrectable pattern configurations and margin-short shapes (marginless points) should be estimated in advance as early as possible, so that design rules, OPC rules, and/or verification rules can be amended to prevent these problems. However, estimation of marginless points in advance entails difficulties, as follows. For example, there is a case where high-accuracy etching simulation is not feasible enough and thus process estimation is difficult to accurately perform. In this case, it is necessary to actually form patterns on a wafer to accurately examine the conversion difference of a process including etching. Further, there is a case where a corrected pattern shape (correction amount) cannot be easily estimated from an input pattern shape. In this case, in order to find marginless points caused after OPC, it is necessary to actually apply an MDP (mask data process) and/or an OPC process to patterns in place of desk experiments, which requires complex calculation and much time. Furthermore, marginless points may generate open/short defects, depending on various combinations of the vertical and horizontal dimensions of shapes. Accordingly, the coordination of pattern categories with correction methods is complex and requires a number of tests for various combinations of pattern configurations.
In consideration of these problems, it is necessary to design a large number of combinations of conceivable test patterns to extract and verify marginless points while performing mask data creation, mask making, transfer onto a wafer, and electron microscope measurement. Consequently, uncorrectable pattern configurations and margin-short shapes even in a corrected state can be found in advance as early as possible, and fed back to design rules, OPC rules, and/or verification rules.
However, variation of pattern configurations that require verification is very broad. Test pattern design can be performed quickly to some extent by an automation tool, but electron microscope measurement entails much manpower and time. Accordingly, in order to perform the measurement within limited time and manpower, the measurement is typically performed only on a limited number of portions, such as portions at and near pattern configurations decided in advance. In this case, outside the measured portions, a hazard pattern or margin-short pattern present may be overlooked, and cannot be suitably fed back to design rules or verification rules. As described above, according to the conventional method, it is difficult to efficiently estimate and/or extract marginless points. Consequently, problems arise such that the TAT of semiconductor manufacturing processes is prolonged because real marginless points are overlooked or extracted with a delay, and/or the process yield is deteriorated due to insufficient process margins of marginless points.